formal equivalence


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Related to formal equivalence: functional equivalence

formal equivalence

n
(Logic) logic the relation that holds between two open sentences when their universal closures are materially equivalent
References in periodicals archive ?
PowerPro is a full suite of RTL power optimization tools featuring new RTL power analysis capabilities, production-proven optimization techniques for reducing dynamic and leakage power in the logic, memory, and embedded processor section of a SoC, and is the only solution that provides sequential formal equivalence checking.
Nida is well known for developing the theory of dynamic equivalence, which he differentiates from formal equivalence or the traditional translation method.
Liturgiam Authenticam, which espouses a formal equivalence approach, recognizes the delicate balancing act that is inherent in a careful translating effort by stating in a dozen instances that the Latin original is to be conveyed in the receiver language "insofar as possible various solutions may be employed.
The PowerPro Platform features new RTL power analysis capabilities, production-proven optimization techniques for reducing dynamic and leakage power in the logic, memory, and embedded processor sections of an SoC, and is the only solution that provides sequential formal equivalence checking.
Synopsys' HECTOR technology has enabled us to perform formal equivalence checking between system-level models and RTL over a range of complex PowerVR cores," said Martin Ashton, vice president of Imagination's PowerVR IP engineering group.
Formal equivalence testing in vervet monkeys has been suggested in order to determine the extent to which vervet calls are semantic (Schusterman, 1990).
Tom has established Calypto as the leading provider of power optimization and formal equivalence technology for SoC design teams," said Aitelli.
The two companies have a long history of successful collaborations that have brought to market full-chip static timing analysis, formal equivalence checking and signal-integrity signoff tools.
Fulfilling the industry requirement for formal equivalence checking, designers can then perform comprehensive functional verification using the Calypto SLEC System-HLS to formally verify equivalence between SystemC ESL models and RTL implementations.
This advanced flow provides a comprehensive solution that includes: RTL lint sign-off; power estimation and exploration; C-to-C formal equivalence checking; C-to-RTL formal equivalence checking; SystemC model generation; and C-to-RTL high-level synthesis, thereby minimizing risk and shortening design cycles with 'real-world' productivity gains of between four and ten times.
The industry requires formal equivalence checking in high-level synthesis flows" states Hisaharu Miwa, general manager of Design Technology Division, LSI Product Technology Unit, Renesas Technology Corp.
The Discovery platform enables power-aware simulation, formal equivalence checking, and static analysis of designs that use modern low-power techniques including multiple power domains, level shifters, isolation cells, and retention memory elements.
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