instruction execution


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Noun1.instruction execution - (computer science) the process of carrying out an instruction by a computer
physical process, process - a sustained phenomenon or one marked by gradual changes through a series of states; "events now in process"; "the process of calcification begins later for boys than for girls"
computer science, computing - the branch of engineering science that studies (with the aid of computers) computable processes and structures
batch processing - the serial execution of computer programs
data processing - (computer science) a series of operations on data by a computer in order to retrieve or transform or classify information
concurrent execution, multiprogramming - the execution of two or more computer programs by a single computer
References in periodicals archive ?
On-site inspections will be carried out in accordance with the Instruction execution eligibility control surface, which is attached as Appendix 2 to the model contract annexed No.
As a combined fixed-and floating-point DSP core capable of instruction by instruction execution of the two processing modes, TI's C66x core achieves even greater performance in an application where each segment of code is executed in its native processing mode.
These capabilities include material reporting, asset management, laboratory data logging, production dispatching, Electronic Batch Record (EBR) management and electronic work instruction execution and workflows.
Also, advanced concepts of speculative instruction execution are presented, comparing hardware and software approaches.
Building on the inherently high throughput of the ARM966E-S core, ST has added high-speed burst Flash memory and zero- latency SRAM for efficient instruction execution and data movement.
In cases where an over-temperature condition is detected, the chip reduces the rate of instruction execution to remain within an acceptable, user-defined temperature envelope.
The performance of the new core was boosted by increasing the number of instruction execution pipeline stages to nine, from five in Toshiba's previous processor core.
The 32-bit RISC core has Harvard architecture, with a five-stage pipeline offering a single cycle instruction execution.
All other vendors handle a failed instruction execution by retrying the instruction in the software.
According to the company, softPLC's instruction execution times on a 486-based system are generally 2 to 10 times faster than conventional PLCs.
7 [micro]s instruction execution time and 140 [micro]s base scan time.
A weighted composite of all of the instruction execution rates for a typical job mix (or benchmark) is a better representation.