A basic 6T SRAM cell consists of two cross-coupled inverters and two access transistors (M5 and M6) are shown in Figure 2(b).
In this section, we present the results of an optimization based method which evaluates the DRV of a 6T SRAM cell incorporating the process parameter variation by considering the variation of [V.sub.t] of four transistors.
The average power consumption of 6T SRAM cell is 46mW and area required is 5[micro][m.sup.2].
For 6T SRAM cell, there are four NMOS and two PMOS are used.
Layout drawn in a 45-nm technology rule shows that the proposed cell occupies 2.02 x greater area as compared with 6T SRAM
VPR  employs a 6T SRAM
cell for LUT configuration and for the overall architecture.
The structure of 6T SRAM
cell is shown in Figure 7.
For the first time, the FinFET-based 6T SRAM
internal nodes behavior is examined by using an array of square wave input of various RC delays and the minimum RC of a functional SRAM cell is acquired.
It also features with very competitive 6T SRAM
and 1T embedded DRAM memory cell sizes.
The traditional 6T SRAM
cell based on SG FinFET devices (SG6T) is shown in Figure 7(a) , where the fin number of the two pull-down transistors must be increased to insure proper read operation.