wait state

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Translations

wait state

n (Comput) → Wartezyklus m; with zero wait statesohne Wartezyklen
References in periodicals archive ?
The higher order address bus and lower order de-multiplexed address bus are concatenated to get a 16 bit address.
Cache interfaces with the processor and main memory via 24-bit address bus, a 32-bit data bus and by command lines further presented.
That way you have a lot more room on the oscilloscope screen to examine the 8/16 traces of the address bus.
The SH7615 processor's hybrid RISC DSP has an extended Harvard Architecture which simultaneously accesses two data and one address bus and also can sustain a multiply-accumulate function in a single-clock cycle.
The chip's interfaces include a 21-bit address bus, 8/16-bit data bus, a general-purpose central processing unit (CPU) interface and a 5 to 25 MHz clock generator interface.
Mr Springborg said the underground project would address bus and rail congestion for an affordable price.
The microcontroller has an 8-bit data bus and a 16-bit address bus, allowing the use of 64KB of external memory.
You want to see what happens, but only after the system receives an interrupt request and then only after 56 clock cycles, but only if a specific 16-bit pattern appeared on a multiplexed address bus during that 56-clock-cycle period.
For example, here is a one-state trigger program containing a single event that tests the Address bus for a value and a single action that triggers the logic analyzer:
Monday's public input forum was designed to address bus riders' concerns about service throughout San Fernando Valley, including issues of overcrowding, aging buses and where new buses should travel.