Decimator


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Dec´i`ma`tor


n.1.One who decimates.
Webster's Revised Unabridged Dictionary, published 1913 by G. & C. Merriam Co.
References in periodicals archive ?
Decimator Design's MD-HX scaler/converter is the kind of gear you have no idea how desperately you need until you arrive at a shoot to find you can't do anything without it.
class="MsoNormalBoneye (left) and Frasha of P-Unit on stage during the Decimator Volume 1 album launch on December 11, 2018.
Music recording powerhouse Decimal Records is set to release its first compilation album, 'Decimator Vol 1'.
The square decimator [[*].sup.2] block [5] is used to calculate the signal energy [E.sub.y] in Equation (17) and [E.sub.z] in Equation (18) from the error signals [e.sub.y] and [e.sub.z] and then put into the SDA blocks.
The first filter is a 4th order low pass Cascaded Integrated-Comb (CIC) decimator filter with a decimation factor of 16.
This type of filter consists of 3 stages: the integrating stage, the decimator or integrator stage, and the comb section.
where n represents acquisition noise, D represents the decimator operator, and H represents the degradation function [7, 12, 13].
The DS or decimator discards (Z -1) number of samples and keeps the remaining samples.
Dolecek, "A new modified comb-rotated sinc (RS) decimator with improved magnitude response," in Proceedings of the 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS '07), pp.
The digital data is received at a sampling clock of 50 MHz and then processed as follows:16 bit high speed ADC Data is passed through a digital Mixer consisting of a 50 MHz Numerically Controlled Oscillator (NCO), a multiplier (16x16 bit), suitable low pass decimation and compensating filters (CIC and CFIR filters) of bandwidth 5 MHz to filter the entire unwanted signal outside the band and a 10 rate decimator to bring down the sampling rate to 5 MS/s for further processing Finally the DDC output will be In phase (I) and Quadrature (Q) signals.
The five subcircuits are reviewed as (i) an input decimator circuit, (ii) an 8-point AI-encoded 1D DCT block for column-wise computation, (iii) an AI-based transposition buffer, (iv) four parallel instantiations of the 8point AI-encoded 1D DCT block for row-wise computation, and (v) the FRS circuit for decoding AI-encoded 2D DCT coefficients.