MOSFET

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MOS·FET

 (mŏs′fĕt′)
n.
A type of semiconductor field effect transistor used in integrated circuit technology that consumes very little power and can be highly miniaturized.

[m(etal)-o(xide)-s(emiconductor) f(ield)-e(ffect) t(ransistor).]
American Heritage® Dictionary of the English Language, Fifth Edition. Copyright © 2016 by Houghton Mifflin Harcourt Publishing Company. Published by Houghton Mifflin Harcourt Publishing Company. All rights reserved.

MOSFET

(ˈmɒsfɛt)
n
(Electronics) electronics metal-oxide-silicon field-effect transistor; a type of IGFET
Collins English Dictionary – Complete and Unabridged, 12th Edition 2014 © HarperCollins Publishers 1991, 1994, 1998, 2000, 2003, 2006, 2007, 2009, 2011, 2014
References in periodicals archive ?
"Most importantly, its NMOS underpinnings allow a third-party system to automatically discover all of the panel's control elements, like its lever keys or touch screens, and assign any desired functionality We are really happy to have the support of some of the key vendors in the industry, and it's great to see manufacturers working hand in hand to deliver real benefits to users across platforms."
Macnica continues to be involved in the NMOS standards and VIPA 25 is a full-stack ST 2110/NMOS solution, supporting all ratified standard subtypes.
If we assume that [g.sub.m1] = [g.sub.m2] = [g.sub.m], NMOS phase shifter gives inverting all-pass function and the PMOS one produces non-inverting all-pass output.
In the condition of constant voltage stress, 2 nm thick oxide NMOS capacitor is stressed with [V.sub.G] = 3.2 V and [V.sub.s] = 0 V in test case (1).
At high to low transition of the input signal di both transistors switch, the PMOS opens and the NMOS goes into high-impedance state.
The NMOS transistor [N.sub.s] provides the biasing current source, which is mirrored from the current source in the bias circuit.
In HS-drain gating technique an additional sleep transistor with sleep input (S) is connected at the output node parallel to the NMOS sleep transistor (S') and PDN.
The difference in our design is the PMOS and NMOS pairs are biased by the tapped node VBIAS from the center-tapped spiral.
The simple resistance only or resistance-capacitance substrate-and-gate triggering NMOS (SGTNMOS) style in 0.18 [micro]m CMOS technology has been investigated and compared with the GGNMOS in detail.
Each includes a very low resistance NMOS pass transistor, and the ISL80113 can deliver an ultra-low 75mV dropout voltage at 3A.
His gates used both nMOS and pMOS transistors, earning the name Complementary Metal Oxide Semiconductor, or CMOS.