parity checking

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par´i`ty check`ing

n.1.(Computers) The process of performing a parity check.
References in periodicals archive ?
The ferroelectric material in F-RAM memory cells is highly resistant to data corruption caused by radiation or magnetic field exposure, providing soft error rate immunity for medical, aerospace and defense applications.
The challenges electronics face at altitude range from capacitor damage to soft error, but these issues are normally reserved for avionics designers.
Topics include defect and fault tolerance (including papers on using architectures for yield improvement and coping with obsolescence), dependability analysis and evaluation (including a network fault model, obtaining microprocessor vulnerability data), hot topics (Trojan horse detection, soft error susceptibility in nanoscale CMOS), design for testability (optimizing full coverage and the impact of default tolerant BIST), reliability and fault tolerance (material fatigue, design-space exploration), error detection and correction (adaptive error control, error detection logic), testing techniques (core chest wrapper design, heuristics-dependent observation), and testing for timing and parametric failures.
of Piraeus, Greece; TIMA laboratory, France; and Intel) present the articles under the following themes: online error detection and correction, self-checking circuits and error detecting codes, radiation hardening techniques, soft error detection and correction methodologies, control-flow checking and fault-tolerance in special applications, fault injection, benchmarking and standardization in software-based SER characterization, mitigation techniques for transient errors, memory self-test and self-repair, posters, reliability and circuit stimulation, networks-on-chip and labs-on-chip, parametric testing techniques, radiation-induced SER, self-test generation techniques, and laser-based fault injection in memories.
Papers from the symposium are presented here, in sections on testing and monitoring for high-quality requirements, SoC infrastructure and testing, advances in RF testing, safe test generation and design validation, memory test, industrial applications, simulation and test generation of delay faults, on-chip resources for mixed-signal devices, solutions for yield enhancement, on-line checking, and soft error mitigation.
Even more expensive are the triple redundancy and voting circuits used to achieve the high levels of soft error immunity needed for aerospace equipment.
In fact, a soft error strike can create an 800 ps noise pulse that could be close to the clock frequency By operating at gate level, this methodology is compliant with any technology process.