superscalar


Also found in: Encyclopedia, Wikipedia.

superscalar

(ˌsuːpəˈskeɪlə)
adj
(Computer Science) (of a computer) performing several tasks at once
References in periodicals archive ?
In contrast to ours, their dynamic tool is only validated on simulation model of multiprocessor chip with four superscalar cores.
Each processor core is a 32-bit superscalar floating point RISC CPUs, capable of performing two floating point operations per clock cycle and one integer calculation per clock cycle.
Prior evaluation of OpenACC compilers and their predecessors was done in 2011 [Compiler and Architecture for Embedded and Superscalar Processors (CAPS), PGI] (Henderson et al.
A CPU-based HPC system is to be implemented - whereby superscalar server CPUs with a high IPC rate are to be offered.
First is the CPU architecture, which expands from a 4-wide superscalar pipeline to a 6-wide design.
(1996).An Out-of-Order Superscalar Processor with Speculative Execution and Fast, Precise Interrupts.
The Denver 2.0 CPU is a seven-way superscalar processor that supports the ARM v8 instruction set.
Woo and Lee [6] extended Amdahl's law for energy-efficient computing of many-core, who classified many-core design styles as three type: symmetric superscalar processor tagged with P*, symmetric smaller power-efficient core tagged with c*, and asymmetric many-core processor with superscalar processor and many smaller cores tagged with P + c*.
On the one hand, the problem of short-circuit current (SCC) superscalar is serious; on the other hand, there are a lot of electromagnetic loops, which lead to the limitations of power transmission capacity.
The sets also sport Amlogic 1.5 Ghz Dual-Core ARM Cortex A9 superscalar processors with 512 MB of DRAM and Dual-Core ARM Mali-400MP2 Graphics Processing Units (GPUs).
- Six stage, superscalar pipeline delivering 2000 Coremarks at 400MHz in a 40LP process
But with Denver on board, longer operating hours are assured due to the chip's "new low latency power-state transitions," that works wonder with the Dynamic Code Optimisation and 7-way Superscalar Design.