HDL

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HDL

 (āch′dē′ĕl′)
n.
A lipoprotein with a relatively high proportion of protein and low proportion of lipids that incorporates cholesterol and transports it to the liver. High levels are associated with a decreased risk of atherosclerosis and coronary artery disease. Also called HDL cholesterol.

[h(igh-)d(ensity) l(ipoprotein).]

HDL

abbreviation for
(Biochemistry) high-density lipoprotein

HDL

high-density lipoprotein: a circulating lipoprotein that picks up cholesterol in the arteries and deposits it in the liver for reprocessing or excretion.
ThesaurusAntonymsRelated WordsSynonymsLegend:
Noun1.HDL - a lipoprotein that transports cholesterol in the blood; composed of a high proportion of protein and relatively little cholesterol; high levels are thought to be associated with decreased risk of coronary heart disease and atherosclerosis
lipoprotein - a conjugated protein having a lipid component; the principal means for transporting lipids in the blood
HDL cholesterol - the cholesterol in high-density lipoproteins; the `good' cholesterol; a high level in the blood is thought to lower the risk of coronary artery disease
Translations

HDL

abbr high density lipoprotein. V. lipoprotein.
References in periodicals archive ?
It has been designed using Verilog and validated using Xilinx Kintex7 FPGA technology.
Prior to the team's work to create hls4ml, physicists would have to manually create simple trigger algorithms, and engineers would then program the FPGAs in Verilog or VHDL.
Developers have traditionally used a hardware description language (HDL) such as VHDL or Verilog to design the FPGA configuration; this requires both coding skills and an in-depth knowledge of the underlying hardware.
The goal of the RTML program is to create a compiler or software platform that can ingest ML frameworks like TensorFlow and Pytorch and, based on the objectives of the specific ML algorithms or systems, generate hardware design configurations and standard Verilog code optimized for the specific need.
For the design block, the use of vendor-neutral tools, specifically HDL (either VHDL or Verilog) is highly desirable.
T&VS is already providing support for System Verilog and UVM Verification activities for a major customer in Noida".
The partial implementation of the proposed architecture on FPGA by writing the Verilog code, allowed the testing of the theoretical conclusions drawn by the author in [8-10] and by
The verilog code for the proposed system was simulated and successfully verified using ModelSim 6.4a and Xilinx 14.1 ISE.
The designs are programmed using the Verilog hardware description language (HDL) and synthesized using Xilinx ISE Simulation software.
The control unit is described in Verilog hardware description language.
After the simulation, the fuzzy rules can be converted to a Verilog code.
Accurate behavioral modeling of opt-electrical sensor in Verilog A.