In pursuing this task, the FTC determined that it "may look to real-world examples of negotiations involving similar technologies." (26) As its "starting point" for determining SDRAM and
DDR SDRAM royalty rates, the FTC used rates contained in Rambus's earlier RDRAM license agreements.
"The DesignWare DDR multiPHY not only offers designers the flexibility to utilize any
DDR SDRAM in the system through simple software control, it also features a power-conscious design that minimizes the silicon area and cost."
Furthermore, even for operating temperatures of 125 degrees-Celsius, these FCRAM products can provide data transfer rates that are more than twice the data rate of conventional
DDR SDRAM memory, while keeping power consumption low.
A value for C load was ascertained assuming that receiver is an Infineon Technologies
DDR SDRAM (32Mbx4), part number HYB25D128400C[C/E/T] in a 66-pin P-TSOPII (plastic thin small outline package Type II).
It comes with a 40 or 80GB hard drive, 512MB
DDR SDRAM, CD drive, built-in Ethernet, FireWire 400, USB ports, and the Mac OS X Tiger.
Up to 32 GB synchronous
DDR SDRAM can be addressed, with expansion units available in 1 GB, 2 GB and 4 GB capacities.
A full gigabyte of onboard
DDR SDRAM allows deep buffering of streaming data at the full 1 Gbps data rate.
The compliment of resources provided on the Virtex-4 ML402 XtremeDSP Evaluation Platform includes a 4VSX35 device, 64 MB
DDR SDRAM, 1 MB ZBT SRAM, 32 MB Compact Flash, 8 MB Flash, 4 kb IIC EEPROM, and 32 Mb Platform Flash.
They are designed to support up to 1.6 TB of storage capacity using high-speed serial ATA drives and Intel's latest 3.2 MHz P4 processor with built-in 800 MHz front side bus and 1 MB cache, and fast 1 GB
DDR SDRAM memory.
With a retail price of just 49,800 yen, the eMachines J2920 comes with a 80GB 7200RPM hard drive, 256MB of
DDR SDRAM and an Intel Celeron D 330 (2.66 GHz) processor.
iReady iSCSI Storage Adapter Features: Single chip ethernetMAX controller; dual DMA channels to bypass the CPU and enable faster data transfer; multiple command and status queues to optimize performance and minimize latency; on-board 1000BaseT PHY to support standard CAT5 for optimal connectivity; 32MB
DDR SDRAM for control block and standard architectures; a 32MB DDR memory for packet buffer memory; Small PCI form factor to minimize real estate; drivers for iSCSI initiator (Linux, Win2K), iSCSI target (Linux only), and SNIA iSCSI APIs