clock cycle


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clock cycle

n. Computers
The interval of time between two pulses of a system clock.
References in periodicals archive ?
To support both high speed and robust data transfer, the devices utilize advanced Rambus-specific features such as Differential Rambus Signal Level (DRSL) interface, which minimizes the signal swing and noise, and Octal Data Rate (ODR) which transfers 8 bits per clock cycle to achieve 3.
With the pipelined architecture, they support clock speeds of up to 200 MHz and provide up to 9 Gbps bandwidth with one clock cycle of initial latency.
In addition, all of the logic blocks are synchronized so that with each clock cycle each logic block completes its specialized, individual task.
This large memory capacity doubles the number of instructions that can be read and executed in one clock cycle.
Advanced Transfer Cache consists of a 256-bit (32 byte) interface that transfers data on each core clock cycle.
By providing the optimum balance of processor clock speed and the amount of work done per clock cycle, the AMD Athlon XP processor 1900+ with QuantiSpeed architecture is an ideal platform to provide our PC enthusiast customers with a superior computing experience.
The microcontroller can operate at clock frequencies up to 200 MHz and, as a result of architectural refinements, is capable of executing most instructions in one clock cycle.