The CPLD has 10,000 usable gates, 512 macrocells, 32

logic array blocks and 172 user I/O pins.

The resultant 8 output blocks becomes individual responses which may be directed to a

logic array for direct response to drive systems or to an MCU embedded algorithm for further analysis.

Integrated circuit composed of configurable interconnects and configurable

logic array by using programmable switches.

Features include a fully connected

logic array where each array input is available to every product term; selectable registers where each flip-flop can be configured as either a T- type or D- type; buried combinatorial feedback where the Q2 register in any macrocell may be bypassed to feed the input back to the

logic array; selectable synchronous/asynchronous clock of any of the flip-flops which allows the registers to use any clock; 48 registers created from two flip-flops per macrocell, each with its own clock and reset and sum terms; and macrocell combinable sum terms where each macrocell's three sum terms may be combined into a single term.

Blast Create SA creates a structured ASIC floorplan of

logic array and physical data to guide the entire implementation process.

Other topics include optimization of the HAS-2 family of hash functions on FPGAs, a space saving layout for passive components, finite state machine implementation with single electron tunneling technology, and a programmable

logic array structure based on quantum-dot cellular automata.

Designed for power-sensitive applications such as notebooks, telecommunications systems and hand-held instrumentation, PZ3032 forms part of the company's CoolRunner product line and incorporates Philips' Fast Zero Power[TM] (FZP) design technique and extended programmable

logic array (XPLA) architecture.

With authorization from LSI, Rochester has the capability to re-create and manufacture the complete silicon-gate HCMOS

logic array product portfolio, which includes more than 10,000 product designs via nine technology nodes ranging from 3 micron to 0.

Currently, acousto-optical systolic computing approaches, SEED-based architectures, spatial light modulator systems employing trinary logic, optical programmable

logic array techniques and holographic optical computing systems are under evaluation.