shift register


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Noun1.shift register - (computer science) register in which all bits can be shifted one or more positions to the left or to the right
register - (computer science) memory device that is the part of computer memory that has a specific address and that is used to hold information of a specific kind
computer science, computing - the branch of engineering science that studies (with the aid of computers) computable processes and structures
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Alfke, "Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators", XILINX, XAPP 052 July 7,1996 (Version 1.1), https://www.xilinx.com/support/documentation/application_notes/xapp052.pdf
602, a "0" is appended in the LSB of the shift register that contains the [bEMG.sub.A] (e.g., element [bEMG.sub.A](0)).
Perhaps because the theory of shift register sequences finds applications in such a broad range of technical fields--among them secure, reliable, and efficient communication; digital ranging and tracking systems; deterministic simulations of random processes; and computer sequencing and timing schemes--it has appeared before now only in disjointed and scattered form, in a variety of now out-of-print or other inaccessible company reports, and in scattered journal articles.
For small area and low power consumption, shift register uses pulsed latch as an striking solution [8].
Senthilkumar, "Modified Version of Playfair Cipher using Linear Feedback Shift Register", International Journal of Computer Science and Network Security, Vol.
Thus the floating point addition/subtraction unit requires the implementation of an 8-bit reversible comparator, an 8-bit reversible subtractor, a 24-bit reversible shift register, a 24-bit reversible carry propagate generate adder, a 24-bit reversible subtractor, a 24-bit reversible comparator and a 32-bit reversible leading zero detector.
According to the proof in [4], if a well-defined random number generator, such as a "Linear Feedback Shift Register" [5], is adopted, the produced integers in the random integer matrix R will be random enough that each generated share image [S.sub.i] dose not contain any information.
The baseband excitation signal is the MLBS which is generated by a high speed digital shift register. The shift register is driven by an RF-clock generator that works at the frequency [f.sub.s].
On all clock cycles where a new value is not being enqueued, the pass shift register values at each stage are compared to the value in the main shift register of the following stage.
In this paper we will propose a novel and practical quantum block encryption algorithm based on a quantum shift register.
Since 12 bits are only read from [Z.sub.0], a multiplexer is needed at the front of [Z.sub.i] Shift Register (SR) in the first iteration to continue filling the registers with 10 zeros (chosen from second multiplexer's input).