(Nasdaq:XLNX), San Jose, Calif., has introduced the new CoolRunner(TM) XPLA3 (eXtended
Programmable Logic Array) CPLD family, which combines an innovative Fast Zero Power (FZP) technology with ultra low standby power (<100 uA) and high device performance (TPD = 5 ns).
Currently, acousto-optical systolic computing approaches, SEED-based architectures, spatial light modulator systems employing trinary logic, optical
programmable logic array techniques and holographic optical computing systems are under evaluation.
Designers use languages such as ABEL and PALASM to generate the files required for programming these PLDs or related
programmable logic arrays (PLAs), programmable array logic (PALs), or generic array logic (GALs).